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IRF6718L2TRPbF IRF6718L2TR1PbF
l l l l l l
PD - 97395B
RoHS Compliant Containing No Lead and Bromide Dual Sided Cooling Compatible Ultra Low Package Inductance Very Low RDS(ON) for Reduced Conduction Losses Optimized for Active O-Ring / Efuse Applications Compatible with existing Surface Mount Techniques
Typical values (unless otherwise specified)
DirectFET Power MOSFET
VDSS
Qg
tot
VGS
Qgd
20nC
RDS(on)
Qgs2
9.4nC
RDS(on)
Qoss
50nC
25V max 20V max 0.50m@10V 1.0m@4.5V
Qrr
67nC
Vgs(th)
1.9V
64nC
Applicable DirectFET Outline and Substrate Outline
S1 S2 SB M2 M4
L6
DirectFET ISOMETRIC
L4
L6
L8
Description
The IRF6718L2TRPbF combines the latest HEXFET(R) Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance in a package that has the footprint of a D-pak. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems. The IRF6718L2TRPbF has extremely low Si Rdson coupled with ultra low package resistance to minimize conduction losses. The IRF6718L2TRPbF has been optimized for parameters that are critical in reliable operation on Active O-Ring / Efuse / hot swap applications.
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 70C ID @ TC = 25C IDM EAS IAR
4
Typical RDS(on) (m)
Max.
Units
V
Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Single Pulse Avalanche Energy Avalanche CurrentAg
g
e e f
h
VGS, Gate-to-Source Voltage (V)
25 20 61 52 270 490 530 49
14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 20 40 60 80 ID= 49A VDS= 20V VDS= 13V
A
mJ A
ID = 61A 3 2 T J = 125C 1 T J = 25C 0 2 4 6 8 10
100 120 140 160 180
VGS, Gate -to -Source Voltage (V)
QG Total Gate Charge (nC)
Fig 1. Typical On-Resistance vs. Gate Voltage
Notes:
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage TC measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.44mH, RG = 25, IAS = 49A.
Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. Surface mounted on 1 in. square Cu board, steady state.
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1
01/26/2010
IRF6718L2TR/TR1PbF
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min.
25 --- --- --- 1.35 --- --- --- --- --- 820 --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units
--- 11 0.50 1.0 1.90 -7.6 --- --- --- --- --- 64 18 9.4 20 16.6 29.4 50 0.90 67 140 47 53 8910 2310 1115 --- ---
Conditions
VGS = 0V, ID = 250A
V mV/C Reference to 25C, ID = 1mA 0.70 m VGS = 10V, ID = 61A i VGS = 4.5V, ID = 49A i 1.4 VDS = VGS, ID = 150A 2.35 V --- 1.0 150 100 -100 --- 96 --- --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 13V = 1.0MHz ns nC
mV/C A nA S VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 13V, ID = 49A VDS = 13V nC VGS = 4.5V ID = 49A See Fig. 18 VDS = 16V, VGS = 0V VDD = 13V, VGS = 4.5V i ID = 49A RG= 6.8
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) g Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge --- --- --- --- --- --- 39 67 490 1.0 59 100 V ns nC
Min.
---
Typ. Max. Units
--- 61 A
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 49A, VGS = 0V i TJ = 25C, IF = 49A di/dt = 200A/s i
Notes:
Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400s; duty cycle 2%.
2
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IRF6718L2TR/TR1PbF
Absolute Maximum Ratings
PD @TA = 25C PD @TA = 70C PD @TC = 25C TP TJ TSTG Power Dissipation Power Dissipation Power Dissipation Peak Soldering Temperature Operating Junction and Storage Temperature Range
e e f
Parameter
Max.
4.3 3.0 83 270 -55 to + 175
Units
W
C
Thermal Resistance
RJA RJA RJA RJC RJ-PCB Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted Linear Derating Factor
e j k fl
Parameter
Typ.
--- 12.5 20 --- 1.0 0.029
Max.
35 --- --- 1.8 ---
Units
C/W
eA
W/C
100 10
Thermal Response ( Z thJA )
1 0.1 0.01
D = 0.50 0.20 0.10 0.05 0.02 0.01
J J 1
R1 R1 2
R2 R2
R3 R3 3
R4 R4 A 4 A
Ri (C/W)
12.2942 14.4246 2.07265 6.20859
18.10679 2.626824 0.007811 0.239314
i (sec)
1
2
3
4
Ci= i/Ri Ci= i/Ri
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc 0.01 0.1 1 10 100 1000
0.0001 1E-006
1E-005
0.0001
0.001
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
(At lower pulse widths ZthJA & ZthJC are combined)
Notes: Mounted on minimum footprint full size board with metalized Surface mounted on 1 in. square Cu board, steady state. TC measured with thermocouple incontact with top (Drain) of part. back and with small clip heatsink. R is measured at TJ of approximately 90C. Used double sided cooling, mounting pad with large heatsink.
Surface mounted on 1 in. square Cu board (still air).
Mounted on minimum footprint full size board with metalized back and with small clip heatsink. (still air)
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IRF6718L2TR/TR1PbF
1000
TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
1000
TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
10
100
1 2.5V 0.1 0.1 1 10 100 1000 VDS, Drain-to-Source Voltage (V)
60s PULSE WIDTH
Tj = 25C
10 0.1
2.5V
60s PULSE WIDTH
Tj = 175C 1 10 100 1000
V DS, Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
1000 VDS = 15V 60s PULSE WIDTH 100
Typical RDS(on) (Normalized)
Fig 5. Typical Output Characteristics
2.0 ID = 61A V GS = 10V V GS = 4.5V 1.5
ID, Drain-to-Source Current (A)
10 T J = 175C T J = 25C 1 T J = -40C
1.0
0.1 1 2 3 4 5
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 6. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd
Fig 7. Normalized On-Resistance vs. Temperature
0.90
Top Vgs = 6.0V Vgs = 8.0V Vgs = 10V Vgs = 12V Vgs = 14V Vgs = 16V Vgs = 18V
T J = 25C
10000
Ciss Coss Crss
Typical RDS(on) ( m)
C oss = C ds + C gd
0.80
Bottom
C, Capacitance(pF)
0.70
1000
0.60
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0.50 0 50 100 150 200
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
Fig 9. Typical On-Resistance vs. Drain Current and Gate Voltage
ID, Drain Current (A)
4
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IRF6718L2TR/TR1PbF
1000
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100sec
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
T J = 175C T J = 25C T J = -40C
1000
100 1msec 10 10msec DC T A = 25C T J = 175C Single Pulse 0.01 0.10 1.00 10.00 100.00
10
1 VGS = 0V 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VSD, Source-to-Drain Voltage (V)
1
0.1
Fig 10. Typical Source-Drain Diode Forward Voltage
70 60
ID, Drain Current (A)
VDS, Drain-to-Source Voltage (V)
Fig 11. Maximum Safe Operating Area
3.0
Typical VGS(th) Gate threshold Voltage (V)
2.5 2.0 1.5 1.0 0.5 0.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) ID = 150A ID = 250A ID = 1.0A
50 40 30 20 10 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
ID = 1.0mA
Fig 12. Maximum Drain Current vs. Case Temperature
400
Gfs, Forward Transconductance (S)
Fig 13. Typical Threshold Voltage vs. Junction Temperature
2400
EAS , Single Pulse Avalanche Energy (mJ)
2000 1600 1200 800 400 0
300 T J = 175C 200 T J = 25C
ID 2.9A 4.6A BOTTOM 49A TOP
100 V DS = 10V 380s PULSE WIDTH
2
0 0 20
40
60
80
100
25
50
75
100
125
150
175
ID,Drain-to-Source Current (A)
Starting T J , Junction Temperature (C)
Fig 14. Typ. Forward Transconductance vs. Drain Current Fig 15. Maximum Avalanche Energy vs. Drain Current
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IRF6718L2TR/TR1PbF
1000 Duty Cycle = Single Pulse 100
Avalanche Current (A)
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming DTj = 150C and Tstart =25C (Single Pulse)
10 0.01 1 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 25C and Tstart = 150C. 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
0.1
0.01 1.0E-06
tav (sec)
Fig 16. Typical Avalanche Current vs.Pulsewidth
600 500 400 300 200 100 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Single Pulse ID = 49A
Notes on Repetitive Avalanche Curves , Figures 16, 17: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 19a, 19b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 16, 17). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
EAR , Avalanche Energy (mJ)
Fig 17. Maximum Avalanche Energy vs. Temperature
6
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IRF6718L2TR/TR1PbF
Id Vds Vgs
L
0
DUT
20K 1K
S
VCC
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
Fig 18a. Gate Charge Test Circuit
Fig 18b. Gate Charge Waveform
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 19b. Unclamped Inductive Waveforms
Fig 19a. Unclamped Inductive Test Circuit
VDS VGS RG
RD
VGS
90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10%
VDS
td(off) tf td(on) tr
Fig 20a. Switching Time Test Circuit
Fig 20b. Switching Time Waveforms
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IRF6718L2TR/TR1PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * di/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 19. Diode Reverse Recovery Test Circuit for N-Channel HEXFET(R) Power MOSFETs
DirectFET Board Footprint, L6 (Large Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
G = GATE D = DRAIN S = SOURCE D D
S D G S
S S
S D S
D
D
8
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IRF6718L2TR/TR1PbF
DirectFET Outline Dimension, L6 Outline (LargeSize Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS METRIC MAX CODE MIN 9.15 A 9.05 7.10 B 6.85 6.00 C 5.90 0.65 D 0.55 0.62 E 0.58 1.22 F 1.18 G 0.98 1.02 0.77 H 0.73 0.42 J 0.38 1.47 K 1.34 2.69 L 2.52 M 0.616 0.676 N 0.020 0.080 0.18 P 0.09 IMPERIAL MIN MAX 0.356 0.360 0.270 0.280 0.232 0.236 0.022 0.026 0.023 0.024 0.046 0.048 0.015 0.017 0.029 0.030 0.015 0.017 0.053 0.058 0.099 0.106 0.0235 0.0274 0.0008 0.0031 0.003 0.007
DirectFET Part Marking
GATE MARKING LOGO PART NUMBER BATCH NUMBER DATE CODE
Line above the last character of the date code indicates "Lead-Free"
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IRF6718L2TR/TR1PbF
DirectFET Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm Std reel quantity is 4000 parts. (ordered as IRF6718L2PBF). REEL DIMENSIONS STANDARD OPTION (QTY 4000) IMPERIAL METRIC MIN CODE MAX MIN MAX 12.992 N.C A 330.0 N.C 0.795 B 20.2 N.C N.C 0.504 C 12.8 0.520 13.2 0.059 D 1.5 N.C N.C E 3.937 100.0 N.C N.C F N.C N.C 0.889 22.4 G 0.646 16.4 0.724 18.4 H 0.626 15.9 0.724 18.4
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package
Data and specifications subject to change without notice. This product has been designed and qualified to MSL1 rating for the Consumer market. Additional storage requirement details for DirectFET products can be found in application note AN1035 on IRs Web site. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.01/2010
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